2+ day, 17+ hour ago   (355+ words) New Micron lab; chip/AI price jump; multi-die monitoring; cryo links for quantum chips; interconnect RC bottleneck; 18A win; CPO roadmap; 2 new CEOs; humanoid readiness gap; Hot Interconnects. In-Depth Deals and Funding New Technologies Security Vehicles, Batteries Trending Video Research Quantum…...

3+ day, 7+ hour ago   (60+ words) Semiconductor Engineering tag: Scope 3 emissions Reducing Scope 3 Value Chain Emissions For Customers Through Sustainability And Innovation Self-Driving Cars Have An Aging Problem Chip Industry Week In Review Copper’s Grip On AI Scaling Is Starting To Slip When Semiconductor Materials Misbehave…...

3+ day, 17+ hour ago   (773+ words) Performance advantage may come down to material choices and precise interconnect decisions. Optimizing the materials and process flows for CFET gate-stack fabrication is a major feat. The next big challenges will be making all the necessary vertical connections between the…...

3+ day, 17+ hour ago   (299+ words) New deep learning models may provide a pathway for modeling warpage. As scaling transistors laterally becomes more difficult, manufacturers are turning to vertical transistor designs such as CFETs and vertical packaging to increase device density. At the same time, the…...

3+ day, 17+ hour ago   (495+ words) Reducing energy consumption is key to both lowering inference cost and enabling emerging physical AI applications. The post Three Strategic Imperatives For Energy-Efficient AI Computing appeared first on Semiconductor Engineering. The headlines are dominated by the unprecedented growth in data…...

3+ day, 17+ hour ago   (563+ words) Semiconductor R&D depends on access to high-quality data, realistic process assumptions, and practical learning from silicon. The post From Research To Production: Collaboration Is Key For Semiconductor Innovation appeared first on Semiconductor Engineering. From Research To Production: Collaboration Is…...

3+ day, 17+ hour ago   (798+ words) By measuring each wafer after lithography and adjusting the next etch step, fabs can pull more wafers back into spec. Semiconductor yield is a constant battle against process variability. Every wafer that falls out of spec represents lost time, lost…...

3+ day, 17+ hour ago   (322+ words) Reducing manufacturing-related emissions may support lowering the embedded carbon footprint of the chips customers use in their products. As data center infrastructure expands to meet growing AI demand, sustainability is becoming an increasingly important consideration for Intel Foundry customers. Companies…...

3+ day, 17+ hour ago   (1776+ words) There is no one-size-fits-all — yet. With HBM4 comes the option of customizing the base die. Memory makers typically design all the layers of an HBM stack, but for a custom base die, who will design it? Who will manufacture it? And…...

4+ day, 17+ hour ago   (257+ words) Power, token cost, interconnects, and software orchestration are pushing data centers toward heterogeneous clusters built from CPUs, GPUs, NPUs, optics, and custom accelerators. SE: Compute clusters comprised of multiple processors acting as a single computer present many design challenges around…...