12+ hour, 54+ min ago  (170+ words) A new technical paper, "In-So IC ESD Protection for Chiplet-Based 3 D Microsystems: Future Research Directions," was published by researchers at the University of California, Riverside. Abstract "Heterogeneous integration opens a pathway to three-dimensional chiplet-based microsystem chips. Electrostatic discharge reliability is…...

13+ hour, 8+ min ago  (330+ words) Semiconductor Engineering Alumina Nanowires Improve Thermal Management in Advanced Packaging (Georgia Tech et al.) A new technical paper, "Epoxy Composites Reinforced with Long Al2 O3 Nanowires for Enhanced Thermal Management in Advanced Semiconductor Packaging," was published by researchers at the Georgia Institute…...

12+ hour, 41+ min ago  (427+ words) Semiconductor Engineering Microarchitecture Tailored to 3 D-Stacked Near-Memory Processing LLM Decoding (U. of Edinburgh, Peking U. , Cambridge et al.) A new technical paper, "Rethinking Compute Substrates for 3 D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design," was published by researchers at University of Edinburgh, Peking University,…...

13+ hour, 34+ min ago  (274+ words) A new technical paper, "Agentic AI-based Coverage Closure for Formal Verification," was published by researchers at Infineon and the NIT Jalandhar. Abstract "Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However,…...

13+ hour, 27+ min ago  (313+ words) A new technical paper, "Chipmunq: A Fault-Tolerant Compiler for Chiplet Quantum Architectures," was published by researchers at the Technical University of Munich. Abstract "As quantum computing advances toward fault-tolerance through quantum error correction, modular chiplet architectures have emerged to provide…...

13+ hour, 40+ min ago  (289+ words) A new technical paper, "Characterisation of Complex Multilayer Nanostructures with High Aspect Ratio," was recent published by researchers at Aalto University, University of Eastern Finland, Chipmetrics OY, and VTT MIKES. Abstract "Deposition studies of deep vertical dips on semiconductor wafers…...

22+ hour, 46+ min ago  (369+ words) Researchers from Binghamton University used commercial parchment paper, commonly used in baking, along with a standard carbon dioxide laser and water-based conductive ink to create disposable, single-use electronic circuits. The laser selectively removes the paper's thin silicone coating in specific…...

1+ day, 22+ hour ago  (1631+ words) The gap between lab performance and fab reality is growing wider as packages grow more complex. It's generally assumed advanced materials will behave the same in the lab as in production, but that assumption is now under serious pressure. But…...

4+ day, 10+ hour ago  (74+ words) Semiconductor Engineering Chip Industry Week In Review Startup Funding: Q1 2026 IC Security Threats Spike With Quantum, AI, And Automotive Memory Wall Gets Higher All AI Data Center Interconnects Will Be Optical Within 5 Years Panel-Level Packaging's Second Wave Meets Engineering Reality AI's…...

4+ day, 22+ hour ago  (642+ words) Marvell's plasmonics buy; Onto's process control stake; TSMC A14/13 and EDA flows; Apple shuffle; LPDDR6; SOCAMM2 chipset; MATCH Act progress; EV resist crunch; India 3 D packaging fab; digital test card for HPC; telemetry platform for power management; edge AI MCU for voice; new…...