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News
Robots can dance; can they work? – Jon Peddie Research
2+ hour, 32+ min ago (200+ words) Figure 1. NXP’s answer is a three-layer neural axis architecture. What do we think? NXP’s systems argument holds up better than most because it names the gaps: Topology discovery and actuator-level safety are real and currently unsolved industry-wide, not marketing inventions....
Intel maps three layers of agentic AI
19+ hour, 40+ min ago (321+ words) Diamond Rapids, Crescent Island, and Wildcat Lake define Intel’s cloud-to-edge agentic AI stack. The disclosed configuration reaches up to 256 new cores and 1.28GB of last-level cache. It supports 16 memory channels at 12,800 MT/s and provides 128 lanes of PCIe Gen6 plus CXL 3.0. Those specifications…...
Intel eyes a return to memory
21+ hour, 41+ min ago (121+ words) Packaging bets replace commodity DRAM ambitions. A packaging comeback, not a DRAM comeback The stacking options on the table The technology Intel already has Intel does not start from zero on packaging. Figure 1. Block diagram of Intel EMIB-T memory. What…...
Micron and Qualcomm chase memory differently
22+ hour, 8+ min ago (486+ words) Two architectures, one memory bottleneck; Infineon and Rambus also have views. Micron builds a wider hierarchy Micron’s recently launched 256GB SOCAMM targets dense, serviceable server builds and gives systems far more memory per CPU than traditional RDIMMs support, running on Micron’s…...
Qualcomm pushes compute next to memory
1+ day, 2+ hour ago (211+ words) High Bandwidth Compute targets the memory wall. Figure 1. Compute capability climbed steeply for generations. Memory bandwidth grew far more slowly, and that gap increasingly sets real-world AI performance. (Source: Qualcomm) Qualcomm’s answer: Move logic next to memory Figure 2. Two philosophies:…...
Qualcomm opens Mojo to challenge CUDA
1+ day, 3+ hour ago (166+ words) Three weeks after a $3.9B deal. For silicon teams evaluating where to invest kernel work, and for CIOs weighing AI infrastructure lock-in, the practical takeaway is the same: the compiler is public now, the license is genuinely permissive, and the pull-request…...
China’s robot boom outpaces its chip independence
3+ day, 22+ hour ago (43+ words) Deployment leads the world; chips still lag. Intel prepares Panther Lake entry handheld chip How do the latest offerings from AMD, Intel, Sony Honda Mobility, and Qualcomm fit into the market? It takes a village to build a Cardinal. © 2026 Jon…...
Unified memory becomes edge AI’s breaking point
6+ day, 2+ hour ago (82+ words) Jon Peddie Research Unified memory becomes edge AI’s breaking point Why memory architecture now decides AI capability. Enjoy full access with a TechWatch subscription! TechWatch is the front line of JPR information gathering service, comprising current stories of interest to…...
Intel prepares Panther Lake entry handheld chip
6+ day, 20+ hour ago (233+ words) New processor targets budget gaming devices soon. Intel is developing a 4+0+4+4 Panther Lake SoC variant specifically for entry-level gaming handhelds, featuring four performance cores, zero efficient cores, four low-power efficiency cores, and four Xe3 GPU cores. This design strategy targets budget-conscious…...
Second-quarter client CPU shipments increased 9.4% from last quarter and were down -1.1% from last year
6+ day, 22+ hour ago (463+ words) Server CPUs were up 8% from last quarter. JPR has released its Q2’26 Overview of PC Client CPUs and iGPUs report, finding that the overall server CPU market increased by 8% quarter to quarter and by 22% year to year. Figure 1. This quarter saw…...