Install
Process & Lithography
Nodes, EUV tools, yield, and the push toward angstrom‑class manufacturing.
- 25 Tracked terms
- Last 30 days Feed window
What this topic collects on
An article joins this feed when it matches these terms. Each one is also a search of its own.
Related topics
Latest in Process & Lithography
Huawei says its new smartphone chip is entirely free of any US-made components
38+ min ago (605+ words) Huawei declared its phones America-free in 2019 Huawei has introduced the Kirin 9050 Pro, a mobile processor that it says is fully free of American technology. The chip powers the Mate XT 2, the third device in the company's tri-fold line, which starts…...
Imec demoes 22nm pitch on single-print high-NA step ⋆ Electronics Weekly
15+ hour, 37+ min ago (244+ words) Imec has demonstrated the feasibility of patterning tight-pitch random logic structures after a CAR-based single-print High NA EUV lithography step. Logic structures include lines/spaces down to 22nm pitch, and vias at 28nm center-to-center distance. This shows that CAR resist technology can…...
Chinese chip tools reach 35% of equipment installed at local fabs
18+ hour, 20+ min ago (135+ words) digitimes Chinese chip tools reach 35% of equipment installed at local fabs Visitors at AMEC's booth during SEMICON China 2026 in Shanghai. Credit: AFP Chinese-made semiconductor equipment accounted for roughly 35% of tools installed at fabs in China in 2025, up from about 25% a…...
ASML and TSMC Just Admitted High-NA EUV Has an Expiration Date
13+ hour, 22+ min ago (30+ words) The September 7 photomask announcement isn’t a packaging upgrade. It’s Intel, Samsung, and TSMC quietly fixing the optical trade …...
[News] Kepler Claims HBM Alternative Without EUV Using GlobalFoundries’ 28nm Fabs, 2027 Production
1+ day, 18+ hour ago (281+ words) As the AI boom strains supply and pushes up costs, startups are exploring new ways to expand memory production. According to TechPowerUp, Kepler Computing claims to have developed an alternative approach to HBM based on a new 3D stacking technique and…...
Samsung Electronics and ASML expand strategic collaboration for next-generation semiconductor manufacturing
1+ day, 22+ hour ago (316+ words) dqindia.com Samsung Electronics and ASML expand strategic collaboration for next-generation semiconductor manufacturing Samsung Electronics further reinforces the leadership with planned high NA EUV adoption for future DRAM manufacturing for the first time in the industry Samsung Electronics and ASML…...
ORNL and Mazak develop hybrid VC-Ez WAAM platform
5+ day, 5+ hour ago (264+ words) The system also integrates an automated palletized transfer system from Mazak, which facilitates the movement of pallets between each production step and reduces the need for operator intervention. The Mazak machining systems are themselves equipped with MAZATROL SmoothEz5 for easy programming…...
Intel reports more than 1 million High-NA wafers—but stitching remains the hurdle
5+ day, 3+ hour ago (1013+ words) Intel reports more than 1 million High-NA wafers, but stitching and mask limits still shape the real manufacturing significance of the milestone. Intel reported in September 2026 that it had processed more than 1,000,000 300-mm wafers through High-NA EUV scanners. That is a…...
[News] Chinese AI Chipmakers Reportedly Hike Prices on HBM Costs, Huawei 950DT Up as Much as 50%
5+ day, 10+ hour ago (461+ words) TrendForce TrendForce News operates independently from our research team, curating key semiconductor and tech updates to support timely, informed decisions. [News] Chinese AI Chipmakers Reportedly Hike Prices on HBM Costs, Huawei 950DT Up as Much as 50% Rising memory costs are adding…...
Zuken-TSMC Alliance Highlights Push Toward Integrated Chiplet Design Workflows
5+ day, 10+ hour ago (47+ words) openPR.com Zuken-TSMC Alliance Highlights Push Toward Integrated Chiplet Design Workflows Press release from: Factmr Permanent link to this press release: You can edit or delete your press release Zuken-TSMC Alliance Highlights Push Toward Integrated Chiplet Design Workflows here...