10+ hour, 21+ min ago  (76+ words) Jon Peddie Research Agentic AI recasts host CPUs Memory and orchestration drive procurement. Enjoy full access with a Tech Watch subscription! Tech Watch is the front line of JPR information gathering service, comprising current stories of interest to the graphics…...

9+ hour, 41+ min ago  (128+ words) Open AI CEO Sam Altman and Broadcom CEO Hock Tan hold the new Jalepe'o chip. (Source: " Open AI) Open AI continues to rely on a diverse silicon ecosystem. Nvidia remains its largest supplier of GPUs, and the company has expanded…...

14+ hour, 48+ min ago  (136+ words) Nano Stack advances dense AI compute. Researcher holding IBM's sub-1 nm node wafer. (Source: IBM) The architecture introduces another scaling option for future AI accelerators, CPUs, networking silicon, and specialized processors. Device engineers gain additional flexibility in floor planning while…...

14+ hour, 12+ min ago  (276+ words) Qualcomm plans to ship its first HBC chip inside the AI250 data center rack in fiscal 2027. Microsoft and Meta have endorsed the architecture through recorded presentations and identified themselves as early adopters of Dragonfly technologies, including HBC and Qualcomm server CPUs....

15+ hour, 50+ min ago  (253+ words) Bolt's Zeus gets noticed, wins Nimbus award for HPC GPU innovation. Bolt Graphics has won the Nimbus Innovation Award for Best HPC GPU Innovation, a useful validation point for a company trying to enter one of the least forgiving markets…...

2+ day, 16+ hour ago  (862+ words) Q. ANT CEO Michael F'rtsch (Source: Q. ANT) Michael F'rtsch: For the moment, we see ourselves as a coprocessor, side-assisting the GPU and the CPU. The workloads we are focused on are the more complex ones'nonlinear functions, for example'because that is where…...

1+ week, 13+ hour ago  (464+ words) nn MAX tiles and Array Linx interconnect deliver 8. 4 TOPS at 16 nm. Then Wang realized the same interconnect architecture that made e FPGA routing efficient could make neural network inference efficient'specifically, it could solve the DRAM bandwidth problem that limits edge…...

1+ week, 2+ day ago  (203+ words) The Jacinto 7 So C integrates an 8 TOPS MMA, C7x DSPs, and ASIL-D safety in one device. The TDA4 VM organizes AI processing across three distinct hardware blocks, each targeting a different layer of the inference pipeline. Figure 1. The full TDA4 VM So C. (Source:…...

1+ week, 3+ day ago  (240+ words) Imagination joins CHASSIS" Automotive Base Die project. The Automotive Base Die is being positioned as the central communication and integration hub for automotive So C infrastructure. It is designed to integrate third-party chiplets using UCIe, the Universal Chiplet Interconnect Express…...

1+ week, 3+ day ago  (347+ words) Bristol's AI chip pioneer trades independence for scale. The first IPU hardware shipped to early access customers in 2018, with the C2 IPU Accelerator PCIe card appearing publicly at ICML in Stockholm, Sweden, that July. Products launched commercially in November 2019. Microsoft joined…...