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News
Chip Industry Week In Review
1+ day, 2+ hour ago (248+ words) Lam Research and ASE expansions; data center shifts; CPO system architecture initiative; 2D-transistor interface solution; USENIX HW security; patent suits; image sensors; programmable AI memtransistor; Nvidia’s new plan; earnings. Semiconductor Engineering published 2 newsletters, 2 special reports, 4 articles, and an opinion piece…...
What Self-Verifying Means In Agentic EDA Workflows And Why It Matters
2+ day, 2+ hour ago (208+ words) Grounding agent decisions in their output is what transforms orchestration into something engineers can build on with confidence. Why does this matter in EDA? In semiconductor and PCB design, there is no room for error and no tolerance for delay....
Vertical Integration Becoming Pervasive
2+ day, 2+ hour ago (306+ words) No system can be optimized without an understanding of both the hardware and software, and to make the right architectural choice requires cooperation. Much of the technology developed at that time has long been abandoned, but remnants do remain, such…...
Copper’s Grip On AI Scaling Is Starting To Slip
2+ day, 2+ hour ago (1684+ words) As AI clusters push beyond rack-scale limits, optical interconnects and circuit switching are reshaping how data centers scale. Scale-up has typically been defined as a single rack with copper interconnect, with programmers using memory semantics. That definition is getting fuzzier....
Is Pergrammable A Word?
2+ day, 2+ hour ago (626+ words) SoC architects need AI silicon that is both highly efficient and fully programmable. But ensuring a solid ROI requires the design team to not only build competitive silicon for today’s known requirements, but also anticipate future needs as markets shift....
Linear Optics And The Push To Scale AI Interconnects
2+ day, 2+ hour ago (351+ words) Move signal processing back onto the host SerDes to reduce system power, latency, and thermal load. AI clusters keep getting larger and more demanding. Training a trillion-parameter model means thousands of accelerators working in lockstep, and at that scale the…...
What Will It Take To Deploy CPO At Scale?
2+ day, 2+ hour ago (720+ words) The path to widespread deployment of co-packaged optics depends on solving challenges in manufacturing, testing, and operations. Co-packaged optics (CPO) is at an inflection point. We see it rapidly transitioning from proof-of-concept prototypes to manufacturable systems. Today, we’re already starting…...
Packet-Based NPUs In The LLM Era: From Compute-Bound CNNs To Memory-Bound Edge And Automotive Workloads
2+ day, 2+ hour ago (496+ words) Vision-only edge processors are giving way to systems where LLMs, VLMs, and generative features sit alongside traditional perception networks. In terms of NPU design, what are the implications when the dominant edge workloads stop being purely compute-bound CNNs and start…...
The 1-Megawatt Rack Debate
2+ day, 2+ hour ago (733+ words) Is it better to cram more compute into each rack or rethink the architecture? Data centers are gearing up for a future in which a single rack could consume as much power as an entire building. Khan says this philosophy…...
DDR5 9600 RDIMMs: Raising The Performance Benchmark For Server Memory
2+ day, 2+ hour ago (208+ words) The ability to move and manage data efficiently is a defining challenge for data center architects. For years, system designers have depended on advances in memory bandwidth to keep pace with growing computational demands. Each generation of server processors has…...